The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

Author: Kazikus Kazirn
Country: Belarus
Language: English (Spanish)
Genre: Technology
Published (Last): 6 March 2009
Pages: 299
PDF File Size: 9.71 Mb
ePub File Size: 10.98 Mb
ISBN: 403-9-67049-643-6
Downloads: 26307
Price: Free* [*Free Regsitration Required]
Uploader: Akinor

It is the Second bit of the select lines. It is the LSB of the select lines. The signal goes low once a conversion is initiated by the start eatasheet and remains low until a conversion is complete. All of the signals are explained below.

ADC Technical Data

You will also need to download multiplex. Modification to the source code are required to use more than just four adc009. This is an address select line for the multiplexer.

The signal can be tie to the ALE signal when the clock frequency is below kHz. Note that it can take up to 2. Once loaded the multiplexer sends the appropriate channel to the converter on the chip. It is the MSB of the select lines. If Dattasheet and ground are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated.


The following control signals are used to control the conversion. Table 2 provides a summary of all of the input and output to the chip. This means it must remain stable for up to 72 clock cycles. C is the most significant bit and A is the least. The clock should conform to the same range as all other control signals. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled.

The maximum clock frequency is affected by the source impedance datashee the analog inputs. As with all control signals it is required to have an input value of Vcc – 1.

The maximum frequence of the clock is 1.

It goes low when a conversion is started and high at the end of a conversion. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA. Clock The clock signal is adc0890 to cycle through the comparator stages to do the conversion.

In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. The minimum pulse width is ns.

Be sure to consult the manufactures data-sheets for other chips. Begin by downloading the files into your desired destination directory and then compile them in this order. This is a bit of the digital converted output. See table 1 for details. For a quick reference refer to table 2.


The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs. That is because ADCs require clocking and can contain control logic including comparators datashret registers. Start The purpose of the start signal acd0809 two fold.

National Semiconductor

Signal from the ADC. This means that an entire conversion takes at least 64 clock cycles. Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals. Address Lines Because the chip has an 8 channel multiplexer there are three address select lines: The other files are enabled register, a register, and a multiplexer.

Top rail of Reference voltage.

Control signal from FPGA. Users can look for a rising edge transition. It is recomended that the source resistance not exceed 5kohms for operation at 1. It can be tied to the Start line if the clock is operated under kHz.