±1 LSB INL; no missing codes. – Programmable throughput up to ksps. – 8 external inputs; programmable as single-ended or differential. Part Number: CF Manufacturer: Silicon Laboratories Description: Microcontrollers (MCU) M Kb 12ADC Download Data Sheet Docket. 2-cycle 16 x 16 MAC engine (CF/1/2/3 and. CF/1/2/3 Refer to the corresponding pages of the datasheet, as indicated in. Table , for a.

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Typical Master Transmitter Sequence Superior performance to emulation systems using. Powering on and Initializing the PLL Timer 2, 3, and 4 Capture Register Low Byte Operating in Multiply and Accumulate Mode Typical Slave Transmitter Sequence Integer and Fractional Math Configuring Timer 2, 3, and 4 to Count Down Instruction Set in 1 or 2 System Clocks. Interrupts and SFR Paging Frame and Transmission Error Detection Internal Oscillator Control Register T0 Mode 0 Block Diagram Timer 2, Timer 3, and Timer Port6 Output Mode Register Port0 Output Mode Register Cache Lock Control Register Timer 1 High Byte Split Mode without Bank Select Cache and Prefetch Optimization On-Board Clock and Reset Configuring the Output Modes of the Port Pins Data Pointer High Byte On-board JTAG debug circuitry allows non-intrusive uses no on-chip resourcesfull speed, in-circuit.


External Memory Interface Pin Assignments Data Pointer Low Byte System Clock Selection Register Crossbar Pin Assignment and Allocation Refer to Table 1. The devices are available in pin TQFP or.

Branch Target Cache Data Flow Oscillator Frequencies for Standard Baud Rates Instruction and CPU Timing Timer 0 High Byte Ports 4 through 7 pin TQFP devices only Crossbar Pin Assignment Example ADC2 Modes of Operation External Oscillator Drive Circuit Port1 Input Mode Register Comparator Functional Block Diagram Multiplexed and Non-multiplexed Selection External 64k Byte Data Memory Interface program.

Timer 2, 3, and 4 Control Registers T0 Mode 2 Block Diagram Global DC Electrical Characteristics Timer 2, 3, and 4 Capture Register High Byte Port Selection and Configuration Highlighted features are listed below.

Ports 0 through 3 and the Priority Crossbar Decoder Configuring the External Memory Interface Split Mode with Bank Select Analog Multiplexer and PGA Extended Interrupt Priority Programming The Flash Memory Typical Slave Receiver Sequence